The present invention relates to integrated circuits, and more particularly, to an electrically erasable and programmable and memory (EEPROM).
EEPROM devices belong to two categories: page programmable memories and word programmable memories. A word generally represents a byte (8 bits), and a page generally represents a set of words belonging to a same word line. Page programmable memories require a high number of programming latches. More particularly, they require as many programming latches as there are bit lines to ensure a simultaneous programming of all the words of a page. In contrast, word programmable memories require a reduced number of latches, for example, eight programming latches for a byte programmable memory.
FIG. 1 schematically illustrates the conventional architecture of a memory MEM1 of the second type, i.e., one that is programmable by word. The memory comprises word lines WLi, bit lines BLj arranged in columns COLk, with each illustrated column comprising eight bit lines BL0 to BL7, and memory cells CEi,j. The memory cells CEi,j are arranged in an array and are connected to the word lines WLi and the bit lines BLj.
Each cell CEi,j comprises a floating gate transistor FGT and an access transistor TA. The access transistor TA has its gate G connected to a word line WLi, its drain D connected to a bit line BLj, and its source S connected to the drain D of transistor FGT. Transistor FGT has its gate G coupled to a column selection line CLk by a gate control transistor CGTi,k, and its source S is connected to a source line SLi. The gate of transistor CGTi,k is connected to word line WLi.
Thus, each group of eight cells CEi,j connected to a word line WLi and to the bit lines BL0 to BL7 of a column COLk forms a word Wi,k that may be selected by the corresponding column selection line CLk and word line WLi. To this effect, the word lines WLi are connected to the outputs of a line decoder RDEC. The column selection lines CLk are connected to latches LSCk delivering a gate control signal CGSk which depends on a column selection signal SELk received as an input. The selection signal SELk is delivered by a column decoder CDEC. Line decoder RDEC and column decoder CDEC receive respectively the most significant bits and the less significant bits of an address AD applied to the memory. Source line SLi may be brought to a floating potential or may be connected to ground by a transistor SLT driven by a signal SLS.
Memory MEM1 also comprises eight programming latches LP0 to LP7, the outputs of which are connected to lines L0 to L7, and eight sense amplifiers SA0 to SA7, the inputs of which are connected to the lines L0 to L7 by read transistors TR0 to TR7 driven by a signal READ. The outputs of amplifiers SA0 to SA7 and the inputs of latches LP0 to LP7 are connected to a data bus DTB, allowing data read in the memory to be delivered by amplifiers SA0 to SA7 or data to be programmed in the memory to be loaded into programming latches LP0 to LP7.
Lines L0 to L7 are coupled to the bit lines BL0 to BL7 of each column COLk by a multiplex bus DMB. Each programming latch LPj of rank j is thus connected to the bit lines of the same rank j present in the columns. To ensure a selective connection of the output of a latch or of the input of a sense amplifier to a predetermined bit line, each bit line BL0-BL7 of each column COLk is provided with a selection amplifier or transistor TSBL0 to TSBL7. Selection transistors TSBL0 to TSBL7 of the bit lines of a same column COLk are driven by a common selection signal BLSk, delivered by a latch LSBLk receiving as an input a column selection signal SELk coming from column decoder CDEC.
There can thus be found in each column of rank k of memory MEM1 a column selection latch LSCk and a bit lines selection latch LSBLk which are driven by a common column selection signal SELk coming from column decoder CDEC. These latches deliver a gate control signal CGSk and a bit line selection signal BLSk. The values of these signals depend on the current operating phase, that is, erasure, programming or reading of a cell.
An erasing or programming operation of a memory cell includes injecting or extracting electrical charges by the Fowler Nordheim effect in the floating gate of the transistor FGT of the cell. An erased transistor FGT has a positive threshold voltage VT1, and a programmed transistor FGT has a negative threshold voltage VT2.
When a reading voltage Vread between VT1 and VT2 is applied to its gate, an erased transistor remains turned OFF, which corresponds by convention to a logic 1, and a programmed transistor is turned ON, which corresponds by convention to a logic 0. The erasing operation is performed by applying an erasing voltage Vpp on the order of 12 to 20 V to the gate G of transistor FGT while source line SLi is brought to ground. The programming operation is performed by applying a programming voltage Vpp to the drain D of transistor FGT by an access transistor TA, while its gate is brought to ground.
During an erasing phase of the memory cells of a word Wi,k, the latch LSCk and the latch LSBLk of the concerned column are activated by signal SELk. Latch LSCk delivers a gate control signal CGSk equal to Vpp, and latch LSBLk delivers a voltage equal to zero (ground). During a programming phase of the memory cells of word Wi,k, latch LSCk delivers a voltage equal to zero (ground) and latch LSBLk delivers voltage Vpp so that the transistors TSBL0 to TSBL7 of the column are turned ON and couple the outputs of the programming latches LPj to the bit lines of the column. During a reading phase of word Wi,k, latch LSCk delivers a reading voltage Vread and latch LSBLk delivers a voltage Vcc so that the transistors TSBL0 to TSBL7 of the column are turned ON and couple the inputs of the sense amplifiers SAj to the bit lines of the column. Read transistors TRj are also turned ON and signal READ is at 1.
As mentioned above, the advantage of such a memory is to have a small number of programming latches, such as the eight latches LP0 to LP7, for example, when a page programmable memory comprises as many programming latches as bit lines. The providing of transistors TSBL0 to TSBL7 is necessary to ensure the connection of a programming latch to a predetermined bit line. The providing of transistors TSBL0 to TSBL7 implies the providing of the latches LSBLk to drive such transistors.
In other words, the bit line selection latches LSBLk make it difficult to reduce the number of programming latches, and complicates the structure of the memory. Thus, for example, a word programmable memory comprising 2048 bit lines arranged in 256 columns must be provided with 256 column selection latches and 256 bit lines selection latches. The latches each comprise a locking element of the selection signal SELk so that the delivered signals CGSk and BLSk remain stable until a reset signal is applied to the latches.
In view of the foregoing background, an object of the present invention is to simplify the architecture of a EEPROM device. The present invention is based on the observation that the locking element comprised in a column selection latch can be used to generate and/or control the selection signal of the bit lines of the column, in addition to the gate control signal provided for the floating gate transistors.
This and other objects, advantages and features according to the present invention are provided by integrating, in a same latch comprising one locking element only, the column selection function and the bit lines selection function. The latch includes two outputs, one for delivering the gate control signal and the other for delivering the bit lines selection signal.
More particularly, the present invention provides an electrically programmable and erasable memory comprising memory cells connected to word lines and bit lines arranged in columns, bit lines selection transistors driven by bit lines selection signals, and column selection latches comprising each a locking element for a column selection signal and means for delivering a gate control signal which depends on the output of the locking element. Each column selection latch comprises means for delivering, in addition to a gate control signal, a bit lines selection signal which depends on the output of the locking element, at least during programming and reading phases of memory cells.
The column selection latch in the active state may deliver, during programming periods of the memory cells, a gate control signal equal to zero and a bit lines selection signal equal or substantially equal to a programming high voltage.
The column selection latch in the active state may deliver, during erasing periods of the memory cells, a gate control signal equal to an erasing high voltage and a bit lines selection signal equal to zero. Alternatively, the column selection latch in the active state may deliver, during erasing periods of memory cells, a gate control signal equal to an erasing high voltage and a bit lines selection signal equal or substantially equal to the erasing high voltage.
The memory may comprise insulating transistors disposed between the bit lines and outputs of the programming latches. The column selection latch may comprise a switching means having a control terminal connected to the output of the locking element, an input terminal receiving a gate control voltage and an output terminal delivering the gate control signal.
The column selection latch may comprise a conductive track, an end of which is connected to the output of the locking element, and the other end of which delivers the bit lines selection signal. The column selection latch may also comprise a second switching means having a control terminal connected to the output of the locking element, an input terminal receiving a predetermined voltage, and an output terminal delivering the bit lines selection signal.
The column selection latch may comprise an inverting gate electrically supplied with a predetermined voltage, the input of which is connected to a node of the locking element and the output of which delivers the bit lines selection signal. The predetermined voltage may be identical to a supply voltage applied to the locking element. Alternatively, the predetermined voltage may be a voltage equal to zero during erasing phases of memory cells.
The present invention also relates to a method of selecting bit lines in an electrically programmable and erasable memory comprising memory cells connected to word lines and bit lines arranged in columns, bit lines selection transistors driven by bit lines selection signals, and column selection latches. Each column selection latch comprises a locking element of a column selection signal, and means for delivering a gate control signal which depends on the output of the locking element. Each column selection latch, in addition to delivering a gate control signal, includes means for delivering a bit lines selection signal which depends on the output of the locking element, at least during programming and reading phases of the memory cells.
The method may comprise providing, in a column selection latch, a switching means having a control terminal connected to the output of the locking element, an input terminal receiving a predetermined voltage, and an output terminal delivering the bit lines selection signal.
The method may comprise providing, in a column selection latch, an inverting gate electrically supplied with a predetermined voltage, the input of and the output of which delivers the bit lines which is connected to a node of the locking element, selection signal. The predetermined voltage may be chosen identical to a supply voltage applied to the locking element. Alternatively, the predetermined voltage may be a voltage equal to zero during erasing phases of memory cells.
The method further comprises providing insulating transistors disposed between the bit lines and outputs of the programming latches.